1. Field of the Invention
The present invention relates to programmable logic arrays (PLAs). More specifically, the present invention relates to sense amplifiers used in programmable array logic (PAL) circuits.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Programmable logic arrays provide `glue logic` for PC (printed circuit) boards. Glue logic is the logic required to interface two boards and generally includes a plurality of AND gates, OR gates and input/output I/O buffers. PLAs consume less space and therefore generally provide glue logic in a less costly manner than individual AND gates, OR gates and I/O buffers.
PLAs also offer the advantage of reconfigurability over discrete or individual gates. That is, PLAs generally include an array of `AND` gates, an array of `OR` gates, and some provision for interconnecting the outputs of selected AND gates to the inputs of selected OR gates. PLAs allow a wide variety of logic functions to be implemented through the combination, via the OR gates, of the product terms, provided by the AND gates. Further, the configuration of the array may be quickly, easily and relatively inexpensively reprogrammed to implement other functions.
As described in U.S. Pat. No. 4,124,899, programmable array logic (PAL) circuits were developed to provide further improvements in the speed, space requirements, cost and power consumption of PLAs. PALs provide programmable AND and fixed OR functions. In a most general sense, a PAL provides a field programmable logic array in which a programmable array of circuit inputs are provided to a plurality of AND gates (cells) to generate product terms. Outputs from subgroups of AND gates are, in turn, nonprogrammably connected as inputs to individual, specified OR gates to provide the sum of products. Sense amplifiers detect state changes in the array and output product terms therefrom.
In many conventional sense amplifiers EE PALs, a fixed or constant reference voltage is used to bias the sense amplifier. The reference voltage is set as a design parameter and is based on the characteristics of the cells in the array. Unfortunately, the cells may be manufactured with characteristics that deviate from a desired specification. In addition, as the cells are programmed and erased repeatedly over time, the characteristics of the cell tend to change. The performance of PAL may therefore be less than optimal due to manufacturing process variations in cell characteristics or changes in cell characteristics due to program and erase cycling.
While conventional sense amplifiers may compensate for the process and temperature variations, conventional sense amplifiers are not known to compensate for cycling variations in EE cell characteristics. Thus, there is a need in the art for a sense amplifier for EE PAL circuits which is capable of properly biasing the cells of the array notwithstanding changes in the characteristics of the cells over time.